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dc.contributor.authorOrtega Otero, Carlosen_US
dc.identifier.otherbibid: 7959712
dc.description.abstractPower gating techniques are effective in mitigating leakage losses, which represent a significant portion of power consumption in nanoscale circuits. We examine variants of two representative techniques, Cut-Off and Zig-Zag Cut-Off [12], and find that they offer an average of 80% and 20% in power savings, respectively, for asynchronous circuit families. We also present a new zero-delay (ZDRTO) wakeup technique for power gated asynchronous pipelines, which leverages the robustness of asynchronous circuits to delays and supply voltage variations. Our ZDRTO technique offers a trade off between wake up time and static power reduction, making it suitable for power gating pipelines with lowduty cycle, bursty usage patterns.en_US
dc.subjectstatic poweren_US
dc.subjectIntegrated Circuitsen_US
dc.titleStatic Power Reduction Techniques For Asynchronous Circuitsen_US
dc.typedissertation or thesisen_US Engineering Universityen_US of Science, Electrical Engineering
dc.contributor.chairManohar, Rajiten_US
dc.contributor.committeeMemberMyers, Andrew C.en_US
dc.contributor.committeeMemberSuh, Gookwon Edwarden_US

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