Engineering design will continue to grow in complexity. The traditional tool of ion, while still very functional, has become more nuanced as design considerations have begun to frequently cross levels of abstraction. As practicing engineers, we must develop tools and methodology to combat the increased complexity of the design process. I propose a general methodology leveraging heuristic optimization to automate design space exploration with a focus on exposing the tradeoffs between metrics of interest. This allows designers to make informed decisions when choosing between competing designs as well as build intuition regarding the design and application space they are working in. While the methodology is useful for all engineering disciplines, I will focus primarily on asynchronous VLSI design in this thesis. To that end, I implemented a research-grade tool called hopTK to aid in the analysis of asynchronous circuits. Given a parameterized circuit, hopTK will sample the design space of that circuit to obtain the Pareto front across metrics of interest-typically energy, area, and throughput. We can then use these Pareto fronts to compare designs and build intuition about said designs. I apply hopTK to two major classes of circuits: communication links and arithmetic logic. I evaluate the major circuit families typical of asynchronous design to find the best-in-class families as well as examining any tradeoffs between circuit families.