Manycore architectures integrate hundreds of cores on a single chip by using simple cores and simple memory systems usually based on software-managed scratchpad memories (SPMs). Such architectures are notoriously challenging to program, since the programmers need to manually manage all aspects of data movement and synchronization for both correctness and performance. This manycore programmability challenge is one of the key barriers to achieving the promise of manycore architectures. This thesis presents both domain-specific (HB-PyTorch and HB-Arc) and general-purpose (HB-Rubick) programming frameworks to address the SPM manycore architecture programmability challenge and/or improve performance. HB-PyTorch enables domain experts to easily accelerate off-the-shelf tensor workloads. Evaluation on three real-world dense and sparse tensor workloads suggests these workloads can achieve approximately 2-6x performance improvement when scaled to a future 2,000-core manycore system compared to an 18-core out-of-order CPU baseline, while potentially achieving higher area-normalized throughput and improved energy-efficiency compared to GPGPUs. HB-Arc explores the potential of decoupled access/execute (DAE) mechanisms, and proposes two software-only techniques, naive-software DAE and systolic-software DAE, along with a lightweight hardware access accelerator for further performance benefit. However, being domain-specific limits their scope. General purpose dynamic task parallel programming frameworks offer many advantages over domain-specific frameworks, including more flexibility and better load-balancing. Conventional wisdom suggests a work-stealing runtime, which forms the core of most dynamic task parallel programming models, is ill-suited for manycore architectures. However, HB-Rubick demonstrates that such a runtime is not just feasible on manycore architectures with SPMs, but it can also significantly improve the performance of irregular workloads when executing on these architectures. The proposed dynamic task parallel programming framework enhanced with three optimizations for leveraging unused SPM space achieves 1.2-28.5x speedup on workloads that benefit from our techniques, and only induces minimal overhead for workloads that do not. This thesis provides a small yet important step towards closing the performance and productivity gap of SPM manycore architectures.