Now showing items 1-2 of 2

    • High Performance Techniques for Reducing Cache Power 

      Bhadauria, Major (2008-04-30)
      Minimizing power consumption continues to grow as a critical design issue for many platforms, from embedded systems to chip multiprocessors (CMP) to ultra scale parallel systems. Embedded systems, like their desktop ...
    • Thread Scheduling For Chip Multiprocessors 

      Bhadauria, Major (2009-10-13)
      Large, high frequency single-core chip designs are increasingly being replaced with larger chip multiprocessor (CMP) designs that tradeoff frequency for greater numbers of cores. Power has become a first-order design ...