Variation Tolerant Calibration Circuits For High Performance I/O
| dc.contributor.author | Mukhopadhyay, Ishita | en_US |
| dc.contributor.chair | Apsel, Alyssa B. | en_US |
| dc.contributor.committeeMember | Manohar, Rajit | en_US |
| dc.contributor.committeeMember | Molnar, Alyosha Christopher | en_US |
| dc.date.accessioned | 2015-04-06T20:13:54Z | |
| dc.date.available | 2020-01-27T07:00:37Z | |
| dc.date.issued | 2015-01-26 | en_US |
| dc.description.abstract | Continuous scaling of CMOS processes leads to increasing integration of digital and analog subsystems on one chip. But the impact of process variation on these analog blocks is more pronounced than on the digital components, which raises the need for accurate calibration circuits in these systems. Current-steering thermometer digital-to-analog converters (DACs) are used as calibration tools in many such high speed I/O systems. As we move towards lower technology nodes, the overall DAC area is decreasing. But this degrades matching and therefore affects the DACs' accuracy. In this work, we propose a dual-calibration technique to improve the matching accuracy and the static linearity of a current-steering thermometer DAC. The novelty of the proposed scheme lies in obtaining the best samples from the error distribution using redundancy for improved matching followed by adaptively reordering these samples to reduce error accumulation. We consider the statistical basis for each of these methods and demonstrate new tools to enable statistical modeling of the proposed technique. Using these tools we demonstrate 36% and 51% reduction in differential non-linearity (DNL) and integral nonlinearity (INL), respectively for an 8-bit current-steering thermometer DAC with two redundant cells per row. This matches well with the Monte Carlo simulations' result - 38% for DNL and 55% for INL. To complete the validation cycle, we fabricated an 8-bit current-steering thermometer DAC with two redundant cells per row in TSMC 65nm CMOS process. We show an improvement of 36% in DNL and 50% in INL from measurement of 16 chips. In I/O systems, it is important to consider the calibration technique's algorithmic complexity too. By normalizing the INL and DNL improvements with complexity, our technique results in better performance compared to other similar existing techniques. We also demonstrate the area benefit of our technique over the baseline case with no calibration and predict that this improvement will only get better as CMOS process technology scales down. Lastly, we show the advantage of using the dual-calibrated DAC in the phase interpolator (PI) of a high speed I/O link model over the use of a baseline DAC in the presence of random variation. | en_US |
| dc.identifier.other | bibid: 9154436 | |
| dc.identifier.uri | https://hdl.handle.net/1813/39348 | |
| dc.language.iso | en_US | en_US |
| dc.subject | digital to analog converter | en_US |
| dc.subject | process variation | en_US |
| dc.subject | calibration | en_US |
| dc.title | Variation Tolerant Calibration Circuits For High Performance I/O | en_US |
| dc.type | dissertation or thesis | en_US |
| thesis.degree.discipline | Electrical Engineering | |
| thesis.degree.grantor | Cornell University | en_US |
| thesis.degree.level | Doctor of Philosophy | |
| thesis.degree.name | Ph. D., Electrical Engineering |
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