Scaling of flash memory cell structures for large-capacity nonvolatile storage will encounter serious technical challenges in lithography, disturbance and gate stack designs. An alternative way to increase the number of bits per unit chip area can be 3-D stacking has caused Due achieved by 3-D stacking of thin-film memory layers. different technology issues that must be overcome before it can be competitive. to the lack of a repeatable and affordable epitaxial growth method, the polycrystalline or amorphous thin films must be deposited with small thermal budget, good transistor quality and minimal parametric variation. The thin-film device geometry must allow reasonable scaling down to 20nm gate pitch. The electrical operation will need to minimize the power consumption and program/erase voltage to avoid reliability problems from temperature and migration due to heat dissipation and defect density concerns in 3-D integration. In this dissertation, we propose new device solutions to support the 3-D stacking memory IC technology. We will first presents the fabrication process, material and electrical characteristics of ultra thin body (UTB) thin-film transistor (TFT) metal nanocrystal memories by using in-situ doped polysilicon chemical vapor deposition (CVD) followed by the chemical mechanical polishing (CMP) process, where surface roughness below 1nm is achieved. The resulting film is about 13nm thick with 1019 cm-3 body doping. SEM and STEM observation demonstrated that size, distribution, and density of nanocrystals could be controlled for electronic device purposes. CBED, 3D tomographic image and EELS analyses also confirmed the physical stability of the nanocrystals. We are able to achieve memory windows of about 1.6V and 2.3V by +/-6V program/erase (P/E) voltages in single and double layer NCs. From these results, it is confirmed that double layer nanocrystal memories demonstrate retention and charge density improvement over single-layer metal nanocrystals due to the increased number density of nanocrystals. To obtain low contact resistance in the source and drain region, we then demonstrate the self-aligned silicidation (SAS) process. The device split without SAS is also shown where the source/drain resistance improvement by SAS can be clearly observed. Retention time characteristics were monitored in the Al2O3/Au/(Ti,Dy)xOy devices with Ni SAS , and were extracted to be well beyond 10 years. Vertical integration of Ge TFT devices is another promising method to achieve 3D integration from the low processing temperature and smaller bandgap. We have obtained a memory window of about 1.8V by +/-5V P/E voltages for UTB Ge TFT with the gate stack of Al2O3/Au/(Ti,Dy)xOy and single layer NCs. Retention characteristics were also satisfactory. From these results, the ultra-thin planar polysilicon or Ge layer, SAS process and the gate stack design contribute to the long retention time and large memory window. Therefore, the demonstrated processes are expected to be applicable for 3D integration to meet high-density flash memory requirements.